Intern Position US Citizen Only
Opportunity:
Intern will learn on-the-job how to develop Verilog Hardware Design Language partitions to translate math functions into an FPGA. Then test them using Partial Reconfiguration to load them into the FPGA. 

Project: 
Develop techniques for inserting proprietary sensor logic into Field Programmable Gate Array (FPGA) and conduct experiments on effectiveness of detecting rogue circuits (Hardware trojan horse) attacks. Create rogue circuits using Verilog Hardware Design Language. 

Start Date  Flexible: early October or early November 
October will allow time to study Verilog language and creation of circuit netlists. 

Period: Start to end of February

Technology Background: 
Design and build environment for testing FPGAs using Partial Reconfiguration.

Tasks:
Using Accord's bitstream loading system (BLS) convert and demonstrate its operations on a standard labtop, including remove access to partial reconfiguration licenses.
Develop partial reconfiguration partition functions for the demonstration of both standard and Galois Field math computations.
Test, Validate and characterize operation of the partitions including resources, power and timing, and placement 
Report ideas and improvements that would improve productivity and operations of the BLS and related partitions. 

Skills: 
System skills to install and operate remote access. 
Standard software development skills in C; 
Prior FPGA experience is a plus but not necessary.
Knowledge of statistical analysis tools and open source tools is a plus.